Anna University COMPUTER ORGANIZATION AND ARCHITECTURE Two marks unit 3
1) Explain MDR and MAR.
The data and address lines of the external memory bus connected to the internal processor bus via the memory data register, MDR, and the memory address register, MAR, respectively. Register MDR has two inputs and two outputs. Data may be loaded into MDR either from the memory bus or from the internal processor bus. The data stored in MDR may be placed on either bus. The input of MAR is connected to the internal bus, and its output is connected to the external bus.
2) Name two special purpose registers.
3) Define datapath.
The registers, the ALU, and the interconnecting bus are collectively referred to as the datapath.
4) Describe the two control signals used for register transfer.
For each register, two control signals are used to place the contents of that register on the bus or to load data on the bus into the register. The input and output of register Ri are connected to the bus via switches controlled by the signals Riin and Riout, respectively. When Riin is set to 1, the data on the bus are loaded into Ri. Similarly, when Riout is set to 1, the contents of register Ri are placed on the bus. While Riout is equal to 0, the bus can be used for transferring data from other registers.
5) Define processor clock.
Processor clock is defined as the time periods in which all operations and data transfers with in the processor take place.
6) What is known as multiphase clocking?
When edge-triggered flip flops are not used, two or more clock signals may be needed to guarantee proper transfer of data. This is known as multiphase clocking.
7) Define MFC.
To accommodate the variability in response time, the processor waits until it receives an indication that the requested read operation has been completed. The control signal used for this purpose is known as Memory-Function-Completed (MFC).
8) What is WMFC.
WMFC is the control signal that causes the processor’s control circuitry to wait for the arrival of the MFC signal.
9) Define register file.
All general purpose registers are combined into a single block called the register file.
10) What is mean by branch instruction.
A branch instruction is an instruction which replaces the contents of the PC with the branch target address. This address is usually obtained by adding an offset X, which is given in the branch instruction, to the updated value of the PC. The location following a branch instruction is called a branch delay slot.
11) What are the two approaches used for generating the control signals in proper sequence?
12) What are the factors determine the control signals?
1.Contents of the control step counter
2.Contents of the instruction register
3.Contents of the condition code flags
4.External input signals, such as MFC and interrupt requests
13) Explain hardwired control.
The control hardwire can be viewed as a state machine that changes from one state to another in every clock cycle, depending on the contents of the instruction register, the condition codes, and the external inputs. The outputs of the state machine are the control signals. The sequence of operations carried out by this machine is determined by the wiring of the logic elements, hence the name “hardwired”.
14) What are the features of the hardwired control.
A controller that uses this approach can operate at high speed. It has little flexibility and the complexity of the instruction set it can implement is limited.
15) What is microprogrammed control?
Microprogrammed control is a scheme in which control signals are generated by a program similar to machine language programs.
16) What is control word?
A control word is a word whose individual bits represent the various control signals.
17) Define microroutine and microinstruction.
A sequence of control words corresponding to the control sequence of a machine instruction constitutes the microroutine for that instruction, and the individual control words in this microroutine are referred to as microinstructions.
18) What is control store?
The microroutines for all instructions in the instruction set of a computer are stored in a special memory called the control store.
19) What is the drawback of assigning one bit position to each control signal?
Assigning individual bits to each control signal results in long microinstructions because the number of required signals is usually large. Moreover, only a few bits are set to 1in any given microinstruction, which means the available bit space is poorly used.
20) Name some register output control signals.
Pcout, MDRout, Zout, Offsetout, R0out, R1out, R2out, R3out, and TEMPout
21) What is vertical organization and horizontal organization?
Highly encoded schemes that use compact codes to specify only a small number of control functions in each microinstruction are referred to as a vertical organization. On the other hand, the minimally encoded scheme in which many resources can be controlled with a single microinstruction is called a horizontal organization.
22) Compare vertical organization and horizontal organization.
23) Explain bit-O-Ring technique.
The micro program shows that branches are not always made to a single branch address. This is a direct consequence of combining simple micro routines by sharing common parts. Consider a point in the microprogram sequencing. At this point, it is necessary to choose between actions required by direct and indirect addressing modes. If the indirect mode is specified in the instruction, then the microinstruction in the location 170 is performed to fetch the operand from the memory. If the direct mode is specified, this fetch must be bypassed by branching immediately to location 171. The most efficient way to bypass microinstruction 170 is to have the preceding branch microinstructions specify the address 170 and then use an OR gate to change the least significant bit of this address to 1if the direct addressing mode is involved. This is known as the bit-Oring technique for modifying branch addresses.
24) Define emulation.
Given a computer with a certain instruction set, it is possible to define additional machine instructions and implement them with extra micro routines. Emulation allows us to replace obsolete equipment with more up to date machines. If the replacement computer fully emulates the original one, then no software changes have to be made to run existing programs. Thus, emulation facilitates transitions to new computer systems with minimal disruption.
25) What is the drawback of microprogrammed control?
It leads to a slower operating speed because of the time it takes to fetch microinstructions from the control store.
26) Define pipelining.
Pipelining is an effective way of organizing concurrent activity in a computer system. The processor executes the program by fetching and executing instructions, one after the other.
27) Name the four steps in pipelining.
Fetch: read the instruction from the memory.
Decode: decode the instruction and fetch the source operand.
Execute: perform the operation specified by the instruction.
Write: store the result in the destination location.
28) What is the use of cache memory?
The use of cache memories solves the memory access problem. In particular, when a cache is included on the same chip as the processor, access time to the cache is usually the same as the time needed to perform other basic operations inside the processor. This makes it possible to divide instruction fetching and processing into steps that are more or less equal in duration. Each of these steps is performed by a different pipeline stages, and the clock period is chosen to correspond to the longest one.
29) What is data hazard?
Any condition that causes the pipeline to stall is called a hazard. A data hazard is any condition in which either the source or the destination operands of an instruction are not available at the time expected in the pipeline. As a result some operation has to be delayed, and the pipeline stalls.
30) What are instruction hazards?
The pipeline may also be stalled because of a delay in the availability of an instruction. For example, this may be a result of a miss in the cache, requiring the instruction to e fetched from the main memory. Such hazards are often called control hazards or instruction hazards.
31) What are called stalls?
An alternative representation of the operation of a pipeline in the case of a cache miss gives the function performed by each pipeline stage in each clock cycle. The periods in which the decode unit, execute unit, and the write unit are idle are called stalls. They are also referred to as bubbles in the pipeline.
32) What is structural hazard?
Structural hazard is the situation when two instructions require the use of a given hardware resource at the same time. The most common case in which this hazard may arise is in access to memory.
33) What is said to be side effect?
When a location other than one explicitly named in an instruction as a destination operand is affected, the instruction is said to have a side effect.
34) What is dispatch unit?
A separate unit which we call the dispatch unit, takes instructions from the front of the queue and sends them to the execution unit. The dispatch unit also performs the decoding function.
35) What is branch folding
The instruction fetch unit has executed the branch instruction concurrently with the execution of other instructions. This technique is referred to as branch folding.
36) What is delayed branching?
A technique called delayed branching can minimize the penalty incurred as a result of conditional branch instructions. The idea is simple. The instructions in the delay slots are always fetched. Therefore, we would like to arrange for them to be fully executed whether or not the branch is taken. The objective is to be able to place useful instructions in these slots. If no useful instructions can be placed in the delay slots, these slots must be filled with NOP instructions.
37) What are condition codes?
In many processors, the condition code flags are stored in the processor status register. They are either set or cleared by many instructions, so that they can be tested by subsequent conditional branch instructions to change the flow of program execution.
38) Define speculative execution.
Speculative execution means that instructions are executed before the processor is certain that they are in the correct execution sequence. Hence, care must be taken that no processor registers or memory locations are updated until it is confirmed that these instructions should indeed be executed. If the branch decision indicates otherwise, the instructions and all their associated data in the execution units must be purged , and the correct instructions fetched and executed.
39) What is called static and dynamic branch prediction?
The branch prediction decision is always the same every time a given instruction is executed. Any approach that has this characteristic is called static branch prediction. Another approach in which the prediction decision may change depending on execution history is called dynamic branch prediction.
40) What are superscalar processors?
Several instructions start execution in the same clock cycle, and the processor is said to use multiple issue. Such processors are capable of achieving an instruction execution throughput of more than one instruction per cycle. They are known as superscalar processors.
41) What is imprecise and precise exception?
Situation in which one or more of the succeeding instructions have been executed to completion is called imprecise exception. Situation in which all subsequent instructions that may have been partially executed are discarded. This is called a precise exception.
42) What is commitment unit?
When out-of-order execution is allowed, a special control unit is needed to guarantee in-order commitment. This is called the commitment unit. It uses a queue called the reorder buffer to determine which instruction should be committed next. Instructions are entered in the queue strictly in program order as they are dispatched for execution.
43) What is a deadlock
A deadlock is a situation that can arise when two units, A and B, use a shared resource. Suppose that unit B cannot complete its task until unit A completes its task. At the same time, unit B has been assigned a resource that unit A needs. If this happens, neither unit can complete its task. Unit A is waiting for the resource it needs, which is being held by unit b. at the same time, unit B is waiting for unit A to finish before it can
release that resource.
PART-B
1.Give the basic organization of a Microprogrammed control unit. Draw a flowchart of a micro routine for the instruction Add Src, Rdst.
2.Draw the organization of a single-bus processor and give the control sequences for fetching a word from memory, storing a word in memory, executing a complete instruction and unconditional and conditional branch.
3.Explain the basic organization of a Hardwired control unit. Mention its advantages and disadvantages.
4.Explain the various types of hazards in pipelining?
5. Write notes on super scalar operation?
6. Explain the multiple bus organization?
7. Explain the techniques used to overcome the various hazards.
8.Explain the classification of data hazards in pipelining?
This technique allows execution of instruction to proceed in the presence of hazards.Tomasulo’s approach allows renaming of registers dynamically. It buffers operands of instructions waiting to issue, fetch them as soon as they are available.
10.Describe about scoreboarding concept.
Scoreboarding is hardware mechanisms that maintain an execution rate of one instruction per cycle by executing an instruction as soon as its operands are made available and no hazard condition prevent it.
Pipelining is an effective way of organizing concurrent activity in a computer system. The processor executes the program by fetching and executing instructions, one after the other.
2) Name the four steps in pipelining.
Fetch: read the instruction from the memory.
Decode: decode the instruction and fetch the source operand.
Execute: perform the operation specified by the instruction.
Write: store the result in the destination location.
3) What is the use of cache memory?
The use of cache memories solves the memory access problem. In particular, when a cache is included on the same chip as the processor, access time to the cache is usually the same as the time needed to perform other basic operations inside the processor. This makes it possible to divide instruction fetching and processing into steps that are more or less equal in duration. Each of these steps is performed by a different pipeline stages, and the clock period is chosen to correspond to the longest one.
4) What is data hazard?
Any condition that causes the pipeline to stall is called a hazard. A data hazard is any condition in which either the source or the destination operands of an instruction are not available at the time expected in the pipeline. As a result some operation has to be delayed, and the pipeline stalls.
5) What are instruction hazards?
The pipeline may also be stalled because of a delay in the availability of an instruction. For example, this may be a result of a miss in the cache, requiring the instruction to e fetched from the main memory. Such hazards are often called control hazards or instruction hazards.
6) What are called stalls?
An alternative representation of the operation of a pipeline in the case of a cache miss gives the function performed by each pipeline stage in each clock cycle. The periods in which the decode unit, execute unit, and the write unit are idle are called stalls. They are also referred to as bubbles in the pipeline.
7) What is structural hazard?
Structural hazard is the situation when two instructions require the use of a given hardware resource at the same time. The most common case in which this hazard may arise is in access to memory.
8) What is said to be side effect?
When a location other than one explicitly named in an instruction as a destination operand is affected, the instruction is said to have a side effect.
9) What is dispatch unit?
A separate unit which we call the dispatch unit, takes instructions from the front of the queue and sends them to the execution unit. The dispatch unit also performs the decoding function.
10) What is branch folding
The instruction fetch unit has executed the branch instruction concurrently with the execution of other instructions. This technique is referred to as branch folding.
11) What is delayed branching?
A technique called delayed branching can minimize the penalty incurred as a result of conditional branch instructions. The idea is simple. The instructions in the delay slots are always fetched. Therefore, we would like to arrange for them to be fully executed whether or not the branch is taken. The objective is to be able to place useful instructions in these slots. If no useful instructions can be placed in the delay slots, these slots must be filled with NOP instructions.
12) What are condition codes?
In many processors, the condition code flags are stored in the processor status register. They are either set or cleared by many instructions, so that they can be tested by subsequent conditional branch instructions to change the flow of program execution.
13) Define speculative execution.
Speculative execution means that instructions are executed before the processor is certain that they are in the correct execution sequence. Hence, care must be taken that no processor registers or memory locations are updated until it is confirmed that these instructions should indeed be executed. If the branch decision indicates otherwise, the instructions and all their associated data in the execution units must be purged , and the correct instructions fetched and executed.
14) What is called static and dynamic branch prediction?
The branch prediction decision is always the same every time a given instruction is executed. Any approach that has this characteristic is called static branch prediction. Another approach in which the prediction decision may change depending on execution history is called dynamic branch prediction.
15) What are superscalar processors?
Several instructions start execution in the same clock cycle, and the processor is said to use multiple issue. Such processors are capable of achieving an instruction execution throughput of more than one instruction per cycle. They are known as superscalar processors.
16) What is imprecise and precise exception?
Situation in which one or more of the succeeding instructions have been executed to completion is called imprecise exception. Situation in which all subsequent instructions that may have been partially executed are discarded. This is called a precise exception.
17) What is commitment unit?
When out-of-order execution is allowed, a special control unit is needed to guarantee in-order commitment. This is called the commitment unit. It uses a queue called the reorder buffer to determine which instruction should be committed next. Instructions are entered in the queue strictly in program order as they are dispatched for execution.
18) What is a deadlock
A deadlock is a situation that can arise when two units, A and B, use a shared resource. Suppose that unit B cannot complete its task until unit A completes its task. At the same time, unit B has been assigned a resource that unit A needs. If this happens, neither unit can complete its task. Unit A is waiting for the resource it needs, which is being held by unit b. at the same time, unit B is waiting for unit A to finish before it canrelease that resource.
UNIT III
PART-A
1) Explain MDR and MAR.
The data and address lines of the external memory bus connected to the internal processor bus via the memory data register, MDR, and the memory address register, MAR, respectively. Register MDR has two inputs and two outputs. Data may be loaded into MDR either from the memory bus or from the internal processor bus. The data stored in MDR may be placed on either bus. The input of MAR is connected to the internal bus, and its output is connected to the external bus.
2) Name two special purpose registers.
- Index register
- Stack pointer
3) Define datapath.
The registers, the ALU, and the interconnecting bus are collectively referred to as the datapath.
4) Describe the two control signals used for register transfer.
For each register, two control signals are used to place the contents of that register on the bus or to load data on the bus into the register. The input and output of register Ri are connected to the bus via switches controlled by the signals Riin and Riout, respectively. When Riin is set to 1, the data on the bus are loaded into Ri. Similarly, when Riout is set to 1, the contents of register Ri are placed on the bus. While Riout is equal to 0, the bus can be used for transferring data from other registers.
5) Define processor clock.
Processor clock is defined as the time periods in which all operations and data transfers with in the processor take place.
6) What is known as multiphase clocking?
When edge-triggered flip flops are not used, two or more clock signals may be needed to guarantee proper transfer of data. This is known as multiphase clocking.
7) Define MFC.
To accommodate the variability in response time, the processor waits until it receives an indication that the requested read operation has been completed. The control signal used for this purpose is known as Memory-Function-Completed (MFC).
8) What is WMFC.
WMFC is the control signal that causes the processor’s control circuitry to wait for the arrival of the MFC signal.
9) Define register file.
All general purpose registers are combined into a single block called the register file.
10) What is mean by branch instruction.
A branch instruction is an instruction which replaces the contents of the PC with the branch target address. This address is usually obtained by adding an offset X, which is given in the branch instruction, to the updated value of the PC. The location following a branch instruction is called a branch delay slot.
11) What are the two approaches used for generating the control signals in proper sequence?
- Hardwired control
- Microprogrammed control
12) What are the factors determine the control signals?
1.Contents of the control step counter
2.Contents of the instruction register
3.Contents of the condition code flags
4.External input signals, such as MFC and interrupt requests
13) Explain hardwired control.
The control hardwire can be viewed as a state machine that changes from one state to another in every clock cycle, depending on the contents of the instruction register, the condition codes, and the external inputs. The outputs of the state machine are the control signals. The sequence of operations carried out by this machine is determined by the wiring of the logic elements, hence the name “hardwired”.
14) What are the features of the hardwired control.
A controller that uses this approach can operate at high speed. It has little flexibility and the complexity of the instruction set it can implement is limited.
15) What is microprogrammed control?
Microprogrammed control is a scheme in which control signals are generated by a program similar to machine language programs.
16) What is control word?
A control word is a word whose individual bits represent the various control signals.
17) Define microroutine and microinstruction.
A sequence of control words corresponding to the control sequence of a machine instruction constitutes the microroutine for that instruction, and the individual control words in this microroutine are referred to as microinstructions.
18) What is control store?
The microroutines for all instructions in the instruction set of a computer are stored in a special memory called the control store.
19) What is the drawback of assigning one bit position to each control signal?
Assigning individual bits to each control signal results in long microinstructions because the number of required signals is usually large. Moreover, only a few bits are set to 1in any given microinstruction, which means the available bit space is poorly used.
20) Name some register output control signals.
Pcout, MDRout, Zout, Offsetout, R0out, R1out, R2out, R3out, and TEMPout
21) What is vertical organization and horizontal organization?
Highly encoded schemes that use compact codes to specify only a small number of control functions in each microinstruction are referred to as a vertical organization. On the other hand, the minimally encoded scheme in which many resources can be controlled with a single microinstruction is called a horizontal organization.
22) Compare vertical organization and horizontal organization.
| Vertical organization | Horizontal organization |
| 1. Highly encoded schemes 2. Specify only a small number of control signals. 3. Operating speed is high. | Minimally encoded schemes Many resources can be controlled. Operating speed is low. |
23) Explain bit-O-Ring technique.
The micro program shows that branches are not always made to a single branch address. This is a direct consequence of combining simple micro routines by sharing common parts. Consider a point in the microprogram sequencing. At this point, it is necessary to choose between actions required by direct and indirect addressing modes. If the indirect mode is specified in the instruction, then the microinstruction in the location 170 is performed to fetch the operand from the memory. If the direct mode is specified, this fetch must be bypassed by branching immediately to location 171. The most efficient way to bypass microinstruction 170 is to have the preceding branch microinstructions specify the address 170 and then use an OR gate to change the least significant bit of this address to 1if the direct addressing mode is involved. This is known as the bit-Oring technique for modifying branch addresses.
24) Define emulation.
Given a computer with a certain instruction set, it is possible to define additional machine instructions and implement them with extra micro routines. Emulation allows us to replace obsolete equipment with more up to date machines. If the replacement computer fully emulates the original one, then no software changes have to be made to run existing programs. Thus, emulation facilitates transitions to new computer systems with minimal disruption.
25) What is the drawback of microprogrammed control?
It leads to a slower operating speed because of the time it takes to fetch microinstructions from the control store.
26) Define pipelining.
Pipelining is an effective way of organizing concurrent activity in a computer system. The processor executes the program by fetching and executing instructions, one after the other.
27) Name the four steps in pipelining.
Fetch: read the instruction from the memory.
Decode: decode the instruction and fetch the source operand.
Execute: perform the operation specified by the instruction.
Write: store the result in the destination location.
28) What is the use of cache memory?
The use of cache memories solves the memory access problem. In particular, when a cache is included on the same chip as the processor, access time to the cache is usually the same as the time needed to perform other basic operations inside the processor. This makes it possible to divide instruction fetching and processing into steps that are more or less equal in duration. Each of these steps is performed by a different pipeline stages, and the clock period is chosen to correspond to the longest one.
29) What is data hazard?
Any condition that causes the pipeline to stall is called a hazard. A data hazard is any condition in which either the source or the destination operands of an instruction are not available at the time expected in the pipeline. As a result some operation has to be delayed, and the pipeline stalls.
30) What are instruction hazards?
The pipeline may also be stalled because of a delay in the availability of an instruction. For example, this may be a result of a miss in the cache, requiring the instruction to e fetched from the main memory. Such hazards are often called control hazards or instruction hazards.
31) What are called stalls?
An alternative representation of the operation of a pipeline in the case of a cache miss gives the function performed by each pipeline stage in each clock cycle. The periods in which the decode unit, execute unit, and the write unit are idle are called stalls. They are also referred to as bubbles in the pipeline.
32) What is structural hazard?
Structural hazard is the situation when two instructions require the use of a given hardware resource at the same time. The most common case in which this hazard may arise is in access to memory.
33) What is said to be side effect?
When a location other than one explicitly named in an instruction as a destination operand is affected, the instruction is said to have a side effect.
34) What is dispatch unit?
A separate unit which we call the dispatch unit, takes instructions from the front of the queue and sends them to the execution unit. The dispatch unit also performs the decoding function.
35) What is branch folding
The instruction fetch unit has executed the branch instruction concurrently with the execution of other instructions. This technique is referred to as branch folding.
36) What is delayed branching?
A technique called delayed branching can minimize the penalty incurred as a result of conditional branch instructions. The idea is simple. The instructions in the delay slots are always fetched. Therefore, we would like to arrange for them to be fully executed whether or not the branch is taken. The objective is to be able to place useful instructions in these slots. If no useful instructions can be placed in the delay slots, these slots must be filled with NOP instructions.
37) What are condition codes?
In many processors, the condition code flags are stored in the processor status register. They are either set or cleared by many instructions, so that they can be tested by subsequent conditional branch instructions to change the flow of program execution.
38) Define speculative execution.
Speculative execution means that instructions are executed before the processor is certain that they are in the correct execution sequence. Hence, care must be taken that no processor registers or memory locations are updated until it is confirmed that these instructions should indeed be executed. If the branch decision indicates otherwise, the instructions and all their associated data in the execution units must be purged , and the correct instructions fetched and executed.
39) What is called static and dynamic branch prediction?
The branch prediction decision is always the same every time a given instruction is executed. Any approach that has this characteristic is called static branch prediction. Another approach in which the prediction decision may change depending on execution history is called dynamic branch prediction.
40) What are superscalar processors?
Several instructions start execution in the same clock cycle, and the processor is said to use multiple issue. Such processors are capable of achieving an instruction execution throughput of more than one instruction per cycle. They are known as superscalar processors.
41) What is imprecise and precise exception?
Situation in which one or more of the succeeding instructions have been executed to completion is called imprecise exception. Situation in which all subsequent instructions that may have been partially executed are discarded. This is called a precise exception.
42) What is commitment unit?
When out-of-order execution is allowed, a special control unit is needed to guarantee in-order commitment. This is called the commitment unit. It uses a queue called the reorder buffer to determine which instruction should be committed next. Instructions are entered in the queue strictly in program order as they are dispatched for execution.
43) What is a deadlock
A deadlock is a situation that can arise when two units, A and B, use a shared resource. Suppose that unit B cannot complete its task until unit A completes its task. At the same time, unit B has been assigned a resource that unit A needs. If this happens, neither unit can complete its task. Unit A is waiting for the resource it needs, which is being held by unit b. at the same time, unit B is waiting for unit A to finish before it can
release that resource.
PART-B
1.Give the basic organization of a Microprogrammed control unit. Draw a flowchart of a micro routine for the instruction Add Src, Rdst.
- Diagram for basic organization
- Explanation
- Flowchart for Add Src, Rdst
2.Draw the organization of a single-bus processor and give the control sequences for fetching a word from memory, storing a word in memory, executing a complete instruction and unconditional and conditional branch.
- Diagram
- Control Sequences
3.Explain the basic organization of a Hardwired control unit. Mention its advantages and disadvantages.
- Diagram for basic organization
- Explanation
- Advantages
- Disadvantages
4.Explain the various types of hazards in pipelining?
- Instruction hazard
- Data hazard
- Structural hazard
- Control hazard
5. Write notes on super scalar operation?
- Explanation
- Diagram
6. Explain the multiple bus organization?
- Explanation
- Diagram
7. Explain the techniques used to overcome the various hazards.
- Structural hazard
- Duplicating resources
- Stalling
- Data hazards
- Stalling
- Duplicating
- Control hazard.
- Predicted taken branch scheme
- Predicted untaken branch scheme
- Flush or freeze technique
- Delayed branch scheme.
8.Explain the classification of data hazards in pipelining?
- RAW - Read After Write (also known as True Data Dependency)
- WAW - Write After Write (also known as Output Dependency)
- WAR - Write After Read (also known as Anti Data Dependency)
This technique allows execution of instruction to proceed in the presence of hazards.Tomasulo’s approach allows renaming of registers dynamically. It buffers operands of instructions waiting to issue, fetch them as soon as they are available.
- Structure of Tomasulo’s system.
- Instruction status
- Register result status
- Reservation station status
10.Describe about scoreboarding concept.
Scoreboarding is hardware mechanisms that maintain an execution rate of one instruction per cycle by executing an instruction as soon as its operands are made available and no hazard condition prevent it.
- Overview of scoreboarding technique
- Instruction status
- Register result status
- Functional unit status
- Limitations of scoreboarding
- RAW hazards cannot be eliminated
2 Marks
1) Define pipelining.Pipelining is an effective way of organizing concurrent activity in a computer system. The processor executes the program by fetching and executing instructions, one after the other.
2) Name the four steps in pipelining.
Fetch: read the instruction from the memory.
Decode: decode the instruction and fetch the source operand.
Execute: perform the operation specified by the instruction.
Write: store the result in the destination location.
3) What is the use of cache memory?
The use of cache memories solves the memory access problem. In particular, when a cache is included on the same chip as the processor, access time to the cache is usually the same as the time needed to perform other basic operations inside the processor. This makes it possible to divide instruction fetching and processing into steps that are more or less equal in duration. Each of these steps is performed by a different pipeline stages, and the clock period is chosen to correspond to the longest one.
4) What is data hazard?
Any condition that causes the pipeline to stall is called a hazard. A data hazard is any condition in which either the source or the destination operands of an instruction are not available at the time expected in the pipeline. As a result some operation has to be delayed, and the pipeline stalls.
5) What are instruction hazards?
The pipeline may also be stalled because of a delay in the availability of an instruction. For example, this may be a result of a miss in the cache, requiring the instruction to e fetched from the main memory. Such hazards are often called control hazards or instruction hazards.
6) What are called stalls?
An alternative representation of the operation of a pipeline in the case of a cache miss gives the function performed by each pipeline stage in each clock cycle. The periods in which the decode unit, execute unit, and the write unit are idle are called stalls. They are also referred to as bubbles in the pipeline.
7) What is structural hazard?
Structural hazard is the situation when two instructions require the use of a given hardware resource at the same time. The most common case in which this hazard may arise is in access to memory.
8) What is said to be side effect?
When a location other than one explicitly named in an instruction as a destination operand is affected, the instruction is said to have a side effect.
9) What is dispatch unit?
A separate unit which we call the dispatch unit, takes instructions from the front of the queue and sends them to the execution unit. The dispatch unit also performs the decoding function.
10) What is branch folding
The instruction fetch unit has executed the branch instruction concurrently with the execution of other instructions. This technique is referred to as branch folding.
11) What is delayed branching?
A technique called delayed branching can minimize the penalty incurred as a result of conditional branch instructions. The idea is simple. The instructions in the delay slots are always fetched. Therefore, we would like to arrange for them to be fully executed whether or not the branch is taken. The objective is to be able to place useful instructions in these slots. If no useful instructions can be placed in the delay slots, these slots must be filled with NOP instructions.
12) What are condition codes?
In many processors, the condition code flags are stored in the processor status register. They are either set or cleared by many instructions, so that they can be tested by subsequent conditional branch instructions to change the flow of program execution.
13) Define speculative execution.
Speculative execution means that instructions are executed before the processor is certain that they are in the correct execution sequence. Hence, care must be taken that no processor registers or memory locations are updated until it is confirmed that these instructions should indeed be executed. If the branch decision indicates otherwise, the instructions and all their associated data in the execution units must be purged , and the correct instructions fetched and executed.
14) What is called static and dynamic branch prediction?
The branch prediction decision is always the same every time a given instruction is executed. Any approach that has this characteristic is called static branch prediction. Another approach in which the prediction decision may change depending on execution history is called dynamic branch prediction.
15) What are superscalar processors?
Several instructions start execution in the same clock cycle, and the processor is said to use multiple issue. Such processors are capable of achieving an instruction execution throughput of more than one instruction per cycle. They are known as superscalar processors.
16) What is imprecise and precise exception?
Situation in which one or more of the succeeding instructions have been executed to completion is called imprecise exception. Situation in which all subsequent instructions that may have been partially executed are discarded. This is called a precise exception.
17) What is commitment unit?
When out-of-order execution is allowed, a special control unit is needed to guarantee in-order commitment. This is called the commitment unit. It uses a queue called the reorder buffer to determine which instruction should be committed next. Instructions are entered in the queue strictly in program order as they are dispatched for execution.
18) What is a deadlock
A deadlock is a situation that can arise when two units, A and B, use a shared resource. Suppose that unit B cannot complete its task until unit A completes its task. At the same time, unit B has been assigned a resource that unit A needs. If this happens, neither unit can complete its task. Unit A is waiting for the resource it needs, which is being held by unit b. at the same time, unit B is waiting for unit A to finish before it canrelease that resource.
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